(1) Field of the Invention
The present invention relates to methods used to fabricate semiconductor devices, and more specifically to a method used to form a dual damascene opening in a stack of insulator layers to expose an underlying conductive gate structure.
(2) Description of the Prior Art
Dual damascene openings formed in insulator layers has enabled conductive via structures as well as overlying conductive interconnect structures to be defined simultaneously in the dual damascene opening. One method of forming a dual damascene opening is to first define a narrow diameter via opening in an entire stack of insulator layers, exposing a top surface of an underlying conductive interconnect structure, followed by definition of a wider diameter trench shape in a top portion of the same insulator layer stack. The above procedure can however result in damage to the top surface of the exposed underlying conductive interconnect structure during the trench definition procedure, resulting in possible higher than desired interface resistance when overlaid with an conductive via structure. In addition other dual damascene opening procedures can also result in loss of insulator thickness as well as corner rounding of the exposed top insulator component of the via opening occurring during various stages of the definition procedure.
The present invention will describe a procedure for formation of a dual damascene opening in a stack of insulator layers in which a critical process step, the step used to remove all stop or liner layers, is accomplished using a two step removal sequence which reduces the risk of corner rounding of an top insulator layer, as well as reducing the risk of damage to an exposed underlying conductive interconnect structure. In addition to the novel two step stop layer removal procedure the present invention will describe etch chemistries and selectivities which also reduce the risk of damage to the underlying conductive interconnect structure during the dual damascene opening procedure. Prior art such as Liu et al, in U.S. Pat. No. 6,211,063 B1, as well as Moise et al, in U.S. Pat. No. 6,211,035 B1, describe methods of forming self aligned conductive structures in a dual damascene opening, as well as simultaneously forming openings to multiple conductive structures located at various levels. These prior art however do not describe the novel process sequence and etch chemistry employed in the present invention for dual damascene openings in an insulator stack in which corner rounding, loss of top insulator layer thickness, as well as damage to an exposed underlying conductive structure, is reduced as a result of the two step stop layer removal procedure.